Work

I joined the renowned BSIM group as a postdoctoral researcher since September 2015. My main job is to maintain, debug and enhance the quality of BSIM models, including:

  • BSIM-CMG (Common Multi-Gate), a model for FinFET and gate-all-around devices
  • BSIM-IMG (Independent Multi-Gate), a model for fully-depleted silicon-on-insulator (FD-SOI) devices with very thin body
  • BSIM-SOI (Silicon-On-Insulator), a model for general SOI devices
  • BSIM-BULK, a charge-based model for planar devices, which has better RF performance
  • BSIM4, a thrshold voltage-based model for planar devices, which is in maintenance mode now

These models are industry all standards approved by Compact Model Coalition (CMC), which we work closely with to meet the needs of members including foundries, EDA vendors, and IC design companies. As a model developer, I regularly report on bug-fixes and enhancements of BSIM models in CMC, where I serve as a representative for the BSIM group. I designed QA testing flow using CMC QA package to ensure the quality of outgoing BSIM models. I also revamped the BSIM website and made several standard releases of BSIM models.

Since December 2016, I become the manager of BSIM group in charge of communication with model users on questions of BSIM models. My goal is to improve the quality of BSIM models in general and enhance the workflow of the BSIM group.

Since February 2016, Prof. Hu and Prof. Salahuddin founded BDMC for compact modeling research besides existing BSIM models. We hold advisory board meetings on campus each year and do many webinars on the BDMC website, which I also help to maintain. We published several papers based on BDMC research. The latest work is on compact modeling of the negative capacitance field effect transistors (NCFETs).

During my four years with TSMC, I worked in the modeling department on production models of the advanced technology nodes. I participated in several baseband (BB) model projects working from silicon data measurment (I-V, C-V, noise) to model parameter extraction to quality assurance (QA) testing. I had know-how in creating corner model and using principal component analysis (PCA) to build statistical model. The projects I joined were broad in scope:

  • Cross-technology: from planar MOSFETs (20-nm) to FinFETs (16-nm/10-nm/7-nm)
  • Cross-device: from core, input/output (IO), to passive devices
  • Cross-threshold voltage (Vt): from standard (svt), low (lvt), to ultra-low (ulvt) threshold voltage
  • Cross-model: from BSIM4 (planar MOSFETs) to BSIM-CMG (FinFETs)
  • Cross-version: from target-driven (version 0.1) to silicon-based (version 1.0) model

I was able to apply my programming skills in C and Verilog-A to this job. I had experiences in maintaining TSMC modeling interface (TMI, written in C) repository and creating modules for new features of the latest technologies. I tested the first few versions of BSIM-CMG standard (written in Verilog-A) and gave feedback to UC Berkeley. Besides regular modeling projects, I also helped managers in answering customer's questions of our production models.

In 2014-2015, I led a small team in developing flicker and thermal noise models for several projects. During this period, I streamlined the workflow and built a modeling platform to reduce the cycle time of production models. In doing so, I learned how to identify problems, set intermediate steps, and collaborate with others toward a reachable goal.

As a result of TSMC's solid training, I am very familiar with using commercial simulators like HSPICE (by Synopsys), Spectre (by Cadence) and writing netlists to do simulation. I am also familiar with process design kit (PDK) and integrated circuit (IC) design flow in general.

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