Publications (Total citations: 142)

Journal papers (12)

  • P. Kushwaha, H. Agarwal, Y.-K. Lin, M.-Y. Kao, J.-P. Duarte, H.-L. Chang, W. Wong, J. Fan, Xiayu, Y. S. Chauhan, S. Salahuddin, and C. Hu, "Modeling of advanced RF bulk FinFETs," IEEE Electron Device Lett., vol. 39, no. 6, pp. 791-794, Jun. 2018. [pdf]

  • H. Agarwal, P. Kushwaha, J. P. Duarte, Y.-K. Lin, A. B. Sachid, M.-Y. Kao, H.-L. Chang, S. Salahuddin, and C. Hu, "Engineering negative differential resistance in NCFETs for analog applications," IEEE Trans. Electron Devices, vol. 65, no. 5, pp. 2033-2039, May 2018. [pdf]

  • H. Agarwal, P. Kushwaha, J. P. Duarte, Y.-K. Lin, A. Sachid, H.-L. Chang, S. Salahuddin, and C. Hu, "Designing 0.5V 5nm HP and 0.23V 5nm LP NC-FinFETs with improved Ioff sensitivity in presence of parasitic capacitance," IEEE Trans. Electron Devices, vol. 65, no. 3, pp. 1211-1216, Mar. 2018. [pdf]

  • Y.-K. Lin, P. Kushwaha, J. P. Duarte, H.-L. Chang, H. Agarwal, S. Khandelwal, A. B. Sachid, M. Harter, J. Watts, Y. S. Chauhan, S. Salahuddin, and C. Hu, "New mobility model for accurate modeling of transconductance in FDSOI MOSFETs," IEEE Trans. Electron Devices, vol. 65, no. 2, pp. 463-469, Feb. 2018. [pdf]

  • Y.-K. Lin, P. Kushwaha, H. Agarwal, H.-L. Chang, J. P. Duarte, A. B. Sachid, S. Khandelwal, S. Salahuddin, and C. Hu, "Modeling of back-gate effects on gate-induced drain leakage and gate currents in UTB SOI MOSFETs," IEEE Trans. Electron Devices, vol. 64, no. 10, pp. 3986-3990, Oct. 2017. [pdf]

  • Y.-K. Lin, J. P. Duarte, P. Kushwaha, H. Agarwal, H.-L. Chang, A. Sachid, S. Salahuddin, and C. Hu, "Compact modeling source-to-drain tunneling in sub-10-nm GAA FinFET with industry standard model," IEEE Trans. Electron Devices, vol. 64, no. 9 pp. 3576-3581, Sep. 2017. [pdf]

  • Y.-K. Lin, S. Khandelwal, J. P. Duarte, H.-L. Chang, S. Salahuddin, and C. Hu, "A predictive tunnel FET compact model with atomistic simulation validation," IEEE Trans. Electron Devices, vol. 64, no. 2, pp. 599-605, Feb. 2017. [pdf]

  • Y.-K. Lin, S. Khandelwal, A. S. Medury, H. Agarwal, H.-L. Chang, Y. S. Chauhan, and C. Hu, "Modeling of subsurface leakage current in low VTH short channel MOSFET at accumulation bias," IEEE Trans. Electron Devices, vol. 63, no. 5, pp. 1840-1845, May 2016. [pdf]

  • C.-M. Lin, Y.-T. Chen, C.-H. Lee, H.-C. Chang, W.-C. Chang, H.-L. Chang, and C. W. Liu, "Voltage linearity improvement of HfO2-based metal–insulator–metal capacitors with H2O prepulse treatment," Journal of The Electrochemical Society, 158 (2) H128-H131, 2011. [pdf]

  • C.-F. Huang, C.-Y. Peng, Y.-J. Yang, H.-C. Sun, H.-C. Chang, P.-S. Kuo, H.-L. Chang, C.-Z. Liu, and C. W. Liu, "Stress-induced hump effects of p-channel polycrystalline silicon thin-film transistors," IEEE Electron Device Lett., vol. 29, no. 12, pp. 1332-1335, Dec. 2008. [pdf]

  • H.-L. Chang, P.-S. Kuo, W.-C. Hua, C.-P. Lin, C.-Y. Lin, and C. W. Liu, "Reduction of crosstalk between dual power amplifiers using laser treatment," IEEE Microw. Wireless Compon. Lett., vol. 18, no. 9, pp. 602-604, Sep. 2008. [pdf]

  • W.-C. Hua, H.-L. Chang, T. Wang, C.-Y. Lin, C.-P. Lin, S. S. Lu, C. C. Meng, and C. W. Liu, "Performance enhancement of the nMOSFET low noise amplifier by package strain," IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 160-162, Jan. 2007. [pdf]

Conference papers (9)

  • J. P. Duarte, S. Khandelwal, A. I. Khan, A. Sachid, Y.-K. Lin, H.-L. Chang, S. Salahuddin, and C. Hu, "Compact models of negative-capacitance FinFETs: Lumped and distributed charge models," in Proc. IEEE International Electron Devices Meeting (IEDM), 30.5.1-30.5.4, Dec. 2016. [pdf]

  • P. Kushwaha, H. Agarwal, Y. S. Chauhan, M. Bhoir, N. R. Mohapatra, S. Khandelwal, J. P. Duarte, Y.-K. Lin, H.-L. Chang, and C. Hu, "Predictive effective mobility model for FDSOI transistors using technology parameters," in Proc. International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 448-451, Aug. 2016. [pdf]

  • H. Agarwal, P. Kushwaha, Y. S. Chauhan, S. Khandelwal, J. P. Duarte, Y.-K. Lin, H.-L. Chang, C. Hu, H. Wu, and P. D. Ye, "Modeling of GeOI and validation with Ge-CMOS inverter circuit using BSIM-IMG industry standard model," in Proc. International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 444-447, Aug. 2016. [pdf]

  • P. Kushwaha, R. Agarwal, H. Agarwal, Y. S. Chauhan, S. Khandelwal, J. P. Duarte, Y.-K. Lin, H.-L. Chang, and C. Hu, "Modeling of threshold voltage for operating point using industry standard BSIM-IMG model," in Proc. International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 216-219, Aug. 2016. [pdf]

  • H.-L. Chang, H.-C. Li, C. W. Liu, F. Chen, and M.-J. Tsai, "A parameterized SPICE macromodel of resistive random access memory and circuit demonstration," in Proc. Simulation of Semiconductor Processes and Devices (SISPAD), pp. 163-166, Sep. 2011. [pdf]

  • H.-L. Chang, H.-C. Li, C. W. Liu, F. Chen, and M.-J. Tsai, "Physical mechanism of HfO2-based bipolar resistive random access memory," in Proc. International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), pp. 110-111, Apr. 2011. [pdf]

  • H.-L. Chang, H.-C. Chang, S.-C. Yang, H.-C. Tsai, H.-C. Li, and C. W. Liu, "Improved SPICE macromodel of phase change random access memory," in Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 134-137, Apr. 2009. [pdf]

  • H.-L. Chang, P.-T. Lin, W.-C. Hua, C.-P. Lin, C.-Y. Lin, C. W. Liu, T.-Y. Yang, and G.-K. Ma, "Differential power combining technique for general power amplifiers using lumped component network," in Proc. Asia-Pacific Microwave Conf. (APMC), pp. 500-503, Dec. 2006. [pdf]

  • W.-C. Hua, P.-T. Lin, C.-P. Lin, C.-Y. Lin, H.-L. Chang, C. W. Liu, T.-Y. Yang, and G.-K. Ma, "Coupling effects of dual SiGe power amplifiers for 802.11n MIMO applications," in Proc. Radio Frequency Integrated Circuits (RFIC) Symp., pp. 65- 68, Jun. 2006. [pdf]

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